• Author : Kaushik Kumar Ram


GUE Decap

Description Generic UDP Encapsulation (GUE) is a general method for encapsulating packets of arbitrary IP protocols within a UDP tunnel. GUE provides an extensible header format with optional data. In this release, decap capability of GUE packets of variant 1 header format has been added. This variant allows direct encapsulation of IPv4/IPV6 in UDP without the GUE header. The inner payload could be one of IPv4, IPv6, or MPLS. But only IPv4 transport is supported. The switch identifies a GUE packet based on the outer UDP destination port. Then it terminates the tunnel based on the outer destination IP and...
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Unconnected Ethernet Interfaces

Switches within the Arista 7050X Series utilize a forwarding chip that goes under the name Trident2. Trident2 is a Switch-on-Chip (SoC) single-chip with support for up to 1280Gbps of forwarding capacity (oversubscribed mode) that is provided by either 32x40G or up to 96x10G+8x40G, or up to 960Gbps (linerate mode). Since some Arista 7050X Series switches provide front-panel ports that use a subset of the capacity available on the SoC, the remaining capacity of the SoC is exposed as “UnconnectedEthernet (Ue)” interfaces to rest of the system. The purpose of exposing these internal ports in this manner is to make them available for...
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VXLAN routing over MLAG

MLAG provides Layer2 active/active redundancy. VXLAN is supported over an MLAG setup by having the two switches implement a single logical VTEP. This means either of the two switches can terminate a single VXLAN tunnel depending on where the packet arrives. VXLAN routing entails routing packets received from a tunnel after decapsulation and/or encapsulating packets into a tunnel after routing. VXLAN bridging is already supported over MLAG. In this release, we have added support for VXLAN routing over MLAG on the 7150 series. While VXLAN bridging enables either of the two switches in the MLAG pair to bridge packets in the overlay,...
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