• Author : Dan Cunningham


Monitoring Link Quality Using Forward Error Correction (FEC) Data on Arista Switches

Introduction When forward error correction is enabled, it provides a set of statistics which can be used to monitor the health of the link at layer 1.  By comparing trends over time it may be possible to predict which links may experience service impacting error rates allowing action to be taken before these events. This document will describe these statistics and how to monitor them on an Arista switch running EOS.   Forward Error Correction Forward error correction (FEC) is a technique used in data communications where data is portioned into blocks and to these blocks parity bits are added. When...
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Arista 7280R Series Systems 10G, 25G, 50G Port Speed Configuration

Description This feature adds support for 10Gb, 25Gb, and 50Gb speeds on additional ports of the 7280QRA-C36S and 7280QR-C72: 7280QRA-C36S: Ports 13 through 23 can now be configured in 4x10G, 4x25G or 2x50G mode.  The paired even numbered ports (ports 14 through 24) are inactive when the first interface of the odd numbered port, physically above it, is configured for 10G or 25G. 7280QR-C72: Ports 11 through 25 and 47 through 61 can now be configured in 4x10G, 4x25G or 2x50G mode.  The paired even numbered ports (ports 12 through 26 and 48 through 62) are inactive when the first...
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QSFP100 Forward Error Correction

Forward Error Correction (FEC) is required with some QSFP100 media to achieve error free operation of the link when running at 100Gbps. This is accomplished by encoding additional parity check bits into the transmitted data at the PHY PCS level. On reception parity is checked and used to correct errors in the received data, if possible, or mark errors which are not correctable.  The process is defined in IEEE 802.3by Clause 91 Reed-Solomon FEC (RS-FEC). Per IEEE802.3 the following media specify the use RS-FEC. 100GBASE-CR4 100GBASE-SR4 100GBASE-AR4 The default behavior of EOS is to enable FEC on media for which the...
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