Posted on January 7, 2015 11:45 pm
 |  Asked by Michael Butash
 |  3239 views
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Hi, I’m working with some lab gear, current an array of 7048T-A and 7124SX switches, and trying to fully understand the hardware architecture to implement efficient enterprise-ish queuing mechanisms for converged infrastructures for pq/wrr-ish behavior.

Problem is, especially on the 1g, replacing cisco’s that are traditionally the trust edge boundary seems impossible when actually coloring traffic, as class map functionality seems unsupported, and using the a dumb “qos dscp x” is simply not suitable with something like a truly untrusted server for a dmz-ish environment.  Main idea is to queue management/control-plane-ish traffic, and provide pq for media.  Sysadmins look at me funny when I tell them to mark packets with dscp at a hypervisor level themselves, and this doesn’t seem to be changing converged ethernet or not.

Is there _any_ way to enforce untrusted port l3/l4 tuple-match coloring for setting dscp on port input at all or are markings assumed by arista to be done entirely on hosts for coloring?

Also, is there a good description how to utilize tail-drop behavior at the platform asic level between the various chips,  the voq’s, vsq’s, and etc, how those relate to data vs. control-plane, traffic-queues, etc?  I’ve not seen anything public or non that gives a good deep-dive on arista qos, about as close is Gary’s Arista Warrior, but still leaves much for someone prodding in catalyst and nexus qos for 15 years.

Thanks in advance!

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Posted by Alexis Dacquay
Answered on February 24, 2015 11:40 pm

Hi  Michael,

About your QoS question: Some platform do support the ACL matching and priority setting, lookup for the feature called ”L3 ACL based DSCP rewrite” in the Release Notes document (Feature Support Matrix). It is available on both some 1G and 10/40G platforms, but not on the 7048T or 7124SX.

About low-level information: The two platforms you mentions are not multi-chip. They have a single network processor, L2/L3 processing is line rate, as well as ACL/QoS features. There is therefore no need for any VoQ (used for high class multi-chip switches).

The ”platform xyz” command would let you see some detailed information, including the queuing to the CPU (varies per platform), this is a good place to investigate on the chip’s information.

 

Just for information, useful resources are :

- For quick feature support: The release notes’ feature matrix

- For feature detailed explanations: the TOI documents customer can access along the new releases

 

Regards,

Alexis

 

 

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